Logic simulator – timing diagrams, glitches and VCD

The DC and transient analyses treat logic gates as analogue parts. The Logic simulator works one level higher. It knows only 0, 1, x (unknown) and z (not driven), and every gate switches a whole number of time units after its inputs change. That is the right view for counters, flip-flops and timing problems. It also runs circuits with hundreds of gates over thousands of clock cycles in a fraction of a second.

Open it with Instruments → Logic simulator…. The dialog opens with the half-adder example and runs it straight away.

Your first netlist

The Netlist box holds the circuit as text, one statement per line:

name Half adder
input A B
output S C
xor U1 S A B delay=2
and U2 C A B delay=1
count A B period=10

An element line has the type, a name, the output net first, then the input nets, and an optional delay=. Flip-flops and other parts with several pins use names, for example dff F1 Q=q D=d CLK=clk RST=reset setup=3. Available types: and or nand nor xor xnor not buf, tri-state bufif1 bufif0 notif1 notif0, mux2 mux4, dlatch srlatch, dff jkff tff, counter and shiftreg (these two need width= and drive a bus).

Inputs need a stimulus:

• clock CLK period=10 duty=0.5 is a clock. It starts low, and its first rising edge comes after the low phase.
• stim A 0:0 15:1 30:x sets values at given times.
• count A B C period=10 steps through every combination, with the first net as the most significant bit.
• const VCC 1 ties a net to a fixed level.

Press Run simulation. The status line reports the simulated time, the number of events and any timing violations. To try different inputs on the same circuit, add lines to Extra stimulus lines (optional).

Reading the timing diagram

Each net gets a lane. A red band means x, and a dashed middle line means z. Counters and shift registers appear as one bus lane with the decimal value. Below the diagram, the Timing table (one row per change) lists every change as text. For circuits without flip-flops and with up to six inputs you also get the Truth table (settled outputs), with the time each row takes to settle.

Load the example 4-bit ripple counter with glitches and press Load example. Every flip-flop switches 2 ns after its clock, so on the way from 7 to 8 the bus shows 6, 4 and 0 before it settles on 8 at 83 ns. Those false values are real glitches. Any logic that decodes the counter directly would see them.

Timing violations

The example Synchronous counter, shift register and a setup violation gives flip-flop FF1 setup=3. Its data input changes 1 ns before the clock edge at 70 ns, so FF1's output becomes x, and the Timing violations table explains why. Real flip-flops would become metastable and settle to a random value. The simulator shows x instead, so you can see which paths are affected.

Building a netlist from your design

• Import gates from the schematic turns every AND, OR, NAND, NOR, XOR and NOT gate of the open circuit into netlist lines. The gate's Propagation delay becomes delay= in nanoseconds. Inputs are stepped through all combinations.
• Build from expression minimises a Boolean expression, such as A'B + AC, with the same Quine–McCluskey method as the truth-table calculator, then builds an AND–OR or OR–AND circuit with gate delays.
• Open netlist file… and Save netlist read and write the netlist as a text file. The netlist stays open in the dialog until you reload the page. It is not saved in the project.

Verilog subset

The Netlist box also accepts one structural Verilog module with single-bit nets, as in the example 2-bit counter in the Verilog subset: input, output, wire and reg declarations, gate primitives such as nand #2 g1 (y, a, b);, assign with & | ^ ~ and ?:, and always @(posedge clk or posedge rst) blocks with <= and if/else. Put the stimuli (clock, stim, count) into Extra stimulus lines (optional). Vectors, parameters, initial blocks and several modules are rejected with the line number.

Exporting

Download VCD writes an IEEE 1364 value change dump for GTKWave, PulseView or Surfer. Download SVG saves the timing diagram, and Download CSV saves the timing table. The same simulation is available as the API and MCP tool ohmforge-logic-simulator. It gives identical waveforms and an identical VCD file for the same netlist.